1. Field of the Invention
The present invention relates generally to digital signal processing systems and more particularly, to first and second logical memory mapping means coupled to first and second digital processors respectively and to a data storage unit for receiving (i) first and second logical addresses generated by the first and second digital processors respectively and (ii) first and second address mapping information respectively, and generating first and second physical addresses such that each of the digital processors can independently access any of a plurality of memory locations within the data storage unit.
2. Description of Related Art
It is well known that applications requiring digital signal processing are expanding tremendously. For example, applications requiring complex real time processing (voice and image processing, pattern and voice recognition, artificial intelligence and scientific computation in general) require filtering (convolution) or correlation operations which are fairly high processor computing power consumers. Digital processing systems are widely utilized for providing information telecommunication services relative to multiple diversely equipped user terminals through high speed digital carrier facilities in a public telecommunication network, and for performing real-time all-digital conversions of signals relative to channels of the digital carrier so as to transmit and receive information in forms associated with user terminal equipment.
For example, U.S. Pat. No. 4,991,169 discloses a telecommunication arrangement for transferring digital information between user data terminals and a processing center (host processor) through a T1 trunk of a common carrier telephone system (public network). The arrangement includes a digital signal processing system between the host processor and the T1 trunk. The public switching network interfaces signals between the user terminals and the T1 trunk. In order to handle the extremely large in-coming and out-going streams of data involved in such arrangements, the system 10 includes two digital signal processors (DSP's) 12 and 14 having a shared instruction memory (IRAM) 16 and a shared data memory (DRAM) 18 as shown in FIG. 1. The system 10 is used to perform, for example, data conversion, convolution and correlation algorithms all of which include table lookup intensive processing.
FIG. 2 shows the DRAM organization used for the system 10 disclosed in U.S. Pat. No. 4,991,169. The DRAM 18 is comprised of 16K address locations and has a word size of 16 bits. DRAM 18 includes a 512 word section 20 for each T1 channel. Up to 24 such sections 20 occupy up to 12,228 words of DRAM 18 for sustaining one T1 line interface. Each section 20 includes work and buffer spaces allocated for reception and transmission processing. DRAM 18 further includes lookup tables comprised of a 3.25K word section 22 for storing filter coefficients, data conversion, etc. and a 512 word section 24 for staging for receive and transmit signaling bits.
The two DSPs 12 and 14 access DRAM 18 in a time interleaved manner when processing information. Each DSP can address up to 32K words (15 bit addressing). Consequently, each DSP 12 and 14 can access the entire DRAM 18. During processing one of the DSPs can perform transmit functions on one channel while the other DSP performs receive operations on an adjacent channel. For example, to process a single byte per channel the system 10 operates in the following manner. DSP 12 accesses data in DRAM transmit work space for channel 1 and links to instruction routines for conversion of data appropriate to the type of data being handled in channel 1. Using these routines, DSP 12 produces a channel byte sample which is stored into the channel 1 transmit buffer space in DRAM 18.
During the foregoing actions performed by DSP 12 above, DSP 14 will be occupying itself with receiving data in another T1 channel (e.g., channel 24). DSP 14 performs this operation by linking to a reception processing routine and accessing data samples currently in DRAM channel 24 receive buffers. DSP 14 then performs conversion processing on received data samples and stores a data byte in the DRAM channel 24 receive work space.
Next, each DSP interrupts the other to transfer processing of outbound data with regard to the channel being processed to the other DSP. More specifically, DSP 14 takes over the handling of outbound data relative to channel 1, links to an instruction routine for transmit interfacing to T1 and passes the data sample formed by DSP 12 over to T1 channel 1. DSP 12 takes over the handling of outbound data relative to channel 24, links to an instruction routine for host interfacing and passes a channel 24 data byte formed by DSP 14 to the host system.
The above-described system suffers from the disadvantage that current table lookup intensive complex digital processing algorithms such as CCITT (International Telegraph and Telephone Consultative Committee) spec V.32 which comprises 9600 bit/s full duplex modems require the DSPs to access large lookup areas and much larger channel spaces using a DRAM that is greater than 32K. In addition, in order to keep complexity and cost to a minimum it is not desirable to increase the number of addressing lines used for each DSP to access the larger DRAM memories required. Thus, there is a need to develop a mapping mechanism for allowing multiple DSPs to share and access more DRAM memory than is logically addressable.